Area efficient in-plane nanomagnetic multiplier and convolution architecture design

Abstract In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to best of author’s knowledge. This complex combinational (nanomagnetic multiplier) proposed is built by exploiting shape, positional hybrid anisotropy and ferromagnetically coupled fixed input majority gate. Subsequently, extend along with NML adder in introducing convolution which efficient terms number nanomagnets, gates clock-cycles. The yields ∼21%–72%, ∼26%–42%, ∼36%–63%, ∼20%–68%, reduction required gate, clock cycles energy compared state-of-the-art designs.